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cy62138f mobl ? 2-mbit (256 k 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-13194 rev. *i revised may 15, 2014 2-mbit (256 k 8) static ram features high speed: 45 ns wide voltage range: 4.5 v to 5.5 v pin compatible with cy62138v ultra low standby power ? typical standby current: 1 ? a ? maximum standby current: 5 ? a ultra low active power ? typical active current: 1.6 ma @ f = 1 mhz easy memory expansion with ce 1 , ce 2 , and oe features automatic power down when deselected complementary metal oxide semiconductor (cmos) for optimum speed and power available in pb-free 32-pin soic and 32-pin thin small outline package (tsop) ii packages functional description the cy62138f is a high performance cmos static ram organized as 256k words by 8 bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications. the device also has an automatic power down feature that significantly re duces power consumption when addresses are not toggling. placing the device into standby mode reduces power consumption by more than 99% when deselected (ce 1 high or ce 2 low). to write to the device, take chip enable (ce 1 low and ce 2 high) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 17 ). to read from the device, take chip enable (ce 1 low and ce 2 high) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins appear on the i/o pins. the eight input and output pins (i/o 0 through i/o 7 ) are placed in a high impedance state when the device is deselected (ce 1 high or ce 2 low), the outputs are disabled (oe high), or during a write operation (ce 1 low and ce 2 high and we low). the cy62138f device is suitable for interfacing with processors that have ttl i/p levels. it is not suitable for processors that require cmos i/p levels. please see electrical characteristics on page 4 for more details and suggested alternatives. logic block diagram
cy62138f mobl ? document number: 001-13194 rev. *i page 2 of 17 contents pin configurations ........................................................... 3 product portfolio .............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 6 data retention waveform ................................................ 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ...................................................................... 11 ordering information ...................................................... 12 ordering code definitions ..... .................................... 12 package diagrams .......................................................... 13 acronyms ........................................................................ 15 documents conventions ............................................... 15 units of measure ....................................................... 15 document history page ................................................. 16 sales, solutions, and legal information ...................... 17 worldwide sales and design s upport ......... .............. 17 products .................................................................... 17 psoc? solutions ...................................................... 17 cypress developer community ................................. 17 technical support ................. .................................... 17
cy62138f mobl ? document number: 001-13194 rev. *i page 3 of 17 pin configurations figure 1. 32-pin soic/tsop ii pinout (top view) 1 2 3 4 5 6 7 8 9 10 11 14 31 32 12 13 16 15 29 30 21 22 19 20 27 28 25 26 17 18 23 24 a 17 a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 v ss v cc ce 2 we oe ce 1 product portfolio product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( ? a) f = 1 mhz f = f max min typ [1] max typ [1] max typ [1] max typ [1] max cy62138fll 4.5 v 5.0 v 5.5 v 45 1.6 2.5 13 18 1 5 note 1. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c.
cy62138f mobl ? document number: 001-13194 rev. *i page 4 of 17 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ............................... ?65 c to + 150 c ambient temperature with power applied ......................................... ?55 c to + 125 c supply voltage to ground potential ............................. ?0.5 v to 6.0 v (v ccmax + 0.5 v) dc voltage applied to outputs in high z state [2, 3] ............. ?0.5 v to 6.0 v (v ccmax + 0.5 v) dc input voltage [2, 3] ......... ?0.5 v to 6.0 v (v ccmax + 0.5 v) output current into outputs (low) ............................ 20 ma static discharge voltage (mil?std?883, method 3015) ..... .............. ........... > 2001 v latch-up current .................................................... > 200 ma operating range device range ambient temperature v cc [4] cy62138fll industrial ?40 c to +85 c 4.5 v to 5.5 v electrical characteristics over the operating range parameter description test conditions 45 ns unit min typ [5] max v oh output high voltage v cc = 4.5 v i oh = ?1.0 ma 2.4 ? ? v v cc = 5.5 v i oh = ?0.1 ma ? ? 3.4 [6] v ol output low voltage i ol = 2.1 ma ? ? 0.4 v v ih input high voltage v cc = 4.5 v to 5.5 v 2.2 ? v cc + 0.5 v v il input low voltage v cc = 4.5 v to 5.5 v ?0.5 ? 0.8 v i ix input leakage current gnd < v i < v cc ?1 ? +1 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc(max) , i out = 0 ma, cmos levels ?1318ma f = 1 mhz ? 1.6 2.5 i sb2 [7] automatic ce power-down current cmos inputs ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = v cc(max) ?15 ? a notes 2. v il(min) = ?2.0 v for pulse durations less than 20 ns. 3. v ih(max) = v cc + 0.75 v for pulse durations less than 20 ns. 4. full device ac operation assumes a 100 ? s ramp time from 0 to v cc (min) and 200 ? s wait time after v cc stabilization. 5. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 6. please note that the maximum v oh limit does not exceed minimum cmos v ih of 3.5 v. if you are interfacing this sr am with 5 v legacy processors that require a minimum v ih of 3.5 v, please refer to application note an6081 for technical details and options you may consider. 7. chip enables (ce 1 and ce 2 ) must be at cmos level to meet the i sb2 / i ccdr spec. other inputs can be left floating.
cy62138f mobl ? document number: 001-13194 rev. *i page 5 of 17 capacitance parameter [8] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance parameter [8] description test conditions 32-pin soic 32-pin tsop ii unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch two-layer printed circuit board 44.53 44.16 ? c/w ? jc thermal resistance (junction to case) 24.05 11.97 ? c/w ac test loads and waveforms figure 2. ac test loads and waveforms parameters 5.0 v unit r1 1800 ? r2 990 ? r th 639 ? v th 1.77 v 3.0 v v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thevenin equivalent all input pulses r th r1 note 8. tested initially and after any design or process changes that may affect these parameters.
cy62138f mobl ? document number: 001-13194 rev. *i page 6 of 17 data retention characteristics over the operating range parameter description conditions min typ [9] max unit v dr v cc for data retention 2.0 ? ? v i ccdr [10] data retention current v cc = v dr , ce 1 > v cc ?? 0.2 v or ce 2 < 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v ?15 ? a t cdr [9] chip deselect to data retention time 0??ns t r [11] operation recovery time 45 ? ? ns data retention waveform figure 3. data retention waveform [12] v cc(min) v cc(min) t cdr v dr > 2.0 v data retention mode t r v cc ce notes 9. tested initially and after any design or process changes that may affect these parameters. typical values are included for re ference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 10. chip enables (ce 1 and ce 2 ) must be at cmos level to meet the i sb2 / i ccdr spec. other inputs can be left floating. 11. full device ac operation requires linear v cc ramp from v dr to v cc(min) > 100 ? s or stable at v cc(min) > 100 ? s. 12. ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high.
cy62138f mobl ? document number: 001-13194 rev. *i page 7 of 17 switching characteristics over the operating range parameter [13, 14] description 45 ns unit min max read cycle t rc read cycle time 45 ? ns t aa address to data valid ? 45 ns t oha data hold from address change 10 ? ns t ace ce 1 low and ce 2 high to data valid ? 45 ns t doe oe low to data valid ? 22 ns t lzoe oe low to low z [15] 5 ? ns t hzoe oe high to high z [15, 16] ? 18 ns t lzce ce 1 low and ce 2 high to low z [15] 10 ? ns t hzce ce 1 high or ce 2 low to high z [15, 16] ? 18 ns t pu ce 1 low and ce 2 high to power-up 0 ? ns t pd ce 1 high or ce 2 low to power-down ? 45 ns write cycle [17, 18] t wc write cycle time 45 ? ns t sce ce 1 low and ce 2 high to write end 35 ? ns t aw address setup to write end 35 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 35 ? ns t sd data setup to write end 25 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high z [15, 16] ? 18 ns t lzwe we high to low z [15] 10 ? ns notes 13. in an earlier revision of this device, under a specific applic ation condition, read and write operations were limited to swi tching of the chip enable signal as described in the application note an66311 . however, the issue has been fixed and in production now, and he nce, this application notes is no longer applicable. it is ava ilable for download on our website as it contains information on the dat e code of the parts, beyond wh ich the fix has been in producti on. 14. test conditions for all parameters other than tri-state paramete rs assume signal transition time of 3 ns (1 v/ns) or less, t iming reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the figure 2 on page 5 . 15. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 16. t hzoe , t hzce , and t hzwe transitions are measured when the outputs enter a high impedance state. 17. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input se tup and hold timing must be referenced to the edge of the sig nal that terminates the write. 18. the minimum write cycle pulse width should be equal to the sum of t hzwe and t sd .
cy62138f mobl ? document number: 001-13194 rev. *i page 8 of 17 switching waveforms figure 4. read cycle 1 (address transition controlled) [19, 20] figure 5. read cycle no. 2 (oe controlled) [20, 21, 22] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd impedance i cc i sb high address ce data out v cc supply current oe notes 19. the device is continuously selected. oe , ce 1 = v il , ce 2 = v ih . 20. we is high for read cycle. 21. address valid before or similar to ce 1 transition low and ce 2 transition high. 22. ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high.
cy62138f mobl ? document number: 001-13194 rev. *i page 9 of 17 figure 6. write cycle no. 1 (we controlled) [23, 24, 25, 26] figure 7. write cycle no. 2 (ce 1 or ce 2 controlled) [23, 24, 25, 26] switching waveforms (continued) data valid t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe address ce we data i/o oe note 27 t wc data valid t aw t sa t pwe t ha t hd t sd t sce address ce data i/o we notes 23. ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 24. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenced to the edge of the sig nal that terminates the write. 25. data i/o is high impedance if oe = v ih . 26. if ce 1 goes high or ce 2 goes low simultaneously with we high, the output remains in high impedance state. 27. during this period, the i/os are in output state. do not apply input signals.
cy62138f mobl ? document number: 001-13194 rev. *i page 10 of 17 figure 8. write cycle no. 3 (we controlled, oe low) [28, 29, 30] switching waveforms (continued) data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe address ce we data i/o note 31 notes 28. ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 29. if ce 1 goes high or ce 2 goes low simultaneously with we high, the output remains in high impedance state. 30. the minimum write cycle pulse width should be equal to the sum of t hzwe and t sd . 31. during this period, the i/os are in output state. do not apply input signals.
cy62138f mobl ? document number: 001-13194 rev. *i page 11 of 17 truth table ce 1 ce 2 we oe inputs/outputs mode power hx [32] x x high z deselect/power-down standby (i sb ) x [32] l x x high z deselect/power-down standby (i sb ) l h h l data out read active (i cc ) l h h h high z output disabled active (i cc ) l h l x data in write active (i cc ) note 32. the ?x? (don?t care) state for the chip enables (ce 1 and ce 2 ) in the truth table refer to the logic state (either high or low). intermediate voltage levels on these pins is not permitted.
cy62138f mobl ? document number: 001-13194 rev. *i page 12 of 17 ordering code definitions ordering information speed (ns) ordering code package diagram package type operating range 45 CY62138FLL-45SXI 51-85081 32-pi n soic (pb-free) industrial contact your local cypress sales repres entative for availability of these parts. temperature grade: i = industrial pb-free package type: xx = s or zs s = 32-pin soic zs = 32-pin tsop ii speed grade: 45 ns ll = low power process technology: f = 90 nm bus width: 8 = 8 density: 3 = 2-mbit family code: 621 = mobl sram family company id: cy = cypress cy 45 xx 621 3 8 f x ll i -
cy62138f mobl ? document number: 001-13194 rev. *i page 13 of 17 package diagrams figure 9. 32-pin soic (450 mils) s32.45/sz32.45 package outline, 51-85081 51-85081 *e
cy62138f mobl ? document number: 001-13194 rev. *i page 14 of 17 figure 10. 32-pin tsop ii (20.95 11.7 6 1.0 mm) zs32 package outline, 51-85095 package diagrams (continued) 51-85095 *b
cy62138f mobl ? document number: 001-13194 rev. *i page 15 of 17 acronyms documents conventions units of measure acronym description cmos complementary metal oxide semiconductor i/o input/output oe output enable soic small outline integrated circuit sram static random access memory tsop thin small outline package we write enable symbol unit of measure c degree celsius mhz megahertz ? a microampere ? s microsecond ma milliampere ns nanosecond ? ohm % percent pf picofarad v volt w watt
cy62138f mobl ? document number: 001-13194 rev. *i page 16 of 17 document history page document title: cy62138f mobl ? , 2-mbit (256 k 8) static ram document number: 001-13194 rev. ecn no. issue date orig. of change description of change ** 797956 see ecn vkn new data sheet. *a 940341 see ecn vkn added footnote #7 related to i sb2 and i ccdr *b 3055174 13/10/2010 rame added acronyms and units of measure . added ordering code definitions . footnotes updated updated package diagram figure 9 and figure 10 . updated as per new template *c 3061313 15/10/2010 rame minor change: corrected ?io? to ?i/o? *d 3232735 04/18/2011 rame removed the note ?for best practice recommendations, refer to the cypress application note ?system design guidelines? at http://www.cypress.com ? in page 1. *e 3287636 06/20/2011 rame updated package diagrams . updated in new template. *f 3846281 12/19/2012 tava updated ordering information (updated part numbers). updated package diagrams : spec 51-85081 ? changed revision from *c to *e. *g 4013949 06/04/2013 memj updated functional description . updated electrical characteristics : added one more test condition ?v cc = 5.5 v, i oh = ?0.1 ma? for v oh parameter and added maximum value corresponding to that test condition. added note 6 and referred the same note in maximum value for v oh parameter corresponding to test condition ?v cc = 5.5 v, i oh = ?0.1 ma?. *h 4099045 08/19/2013 vini updated switching characteristics : added note 13 and referred the same note in ?parameter? column. updated in new template. *i 4380445 05/15/2014 nile updated switching characteristics : added note 18 and referred the same note in ?write cycle?. updated switching waveforms : added note 30 and referred the same note in figure 8 . completing sunset review.
document number: 001-13194 rev. *i revised may 15, 2014 page 17 of 17 mobl is a registered trademark, and more battery life is a trademark, of cypress semiconductor. all products and company names mentioned in this document may be the trademarks of their respective holders. cy62138f mobl ? ? cypress semiconductor corporation, 2007-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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